Stacked semiconductor chips have greater power consumption and higher operating temperatures in comparison with conventional non-stacked integrated circuits. This higher temperature and power consumption can be problematic. For example, the relatively high operating temperatures associated with stacking a dynamic random access memory (DRAM) die on a high-power System-on-Chip (SoC) may result in erasing the data stored in the DRAM. Conventional systems use bulky and expensive heat-sink structures to handle the high temperatures caused by stacked chips. These bulky structures have relatively larger form factors that mitigate to some extent the size advantages that result from stacking integrated circuits.
The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent that it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.